Advanced Packaging Methods
Flip Chip on Leadframe (FCOL) Flip Chip on Substrate (FCOS) Thermal Compression Bonding (TCB)

Flip Chip on Leadframe (FCOL)
APS has developed a proprietary FCOL assembly technology using Pillar Bump that seriously challenges the cost of conventional wire bond process while reaping the full benefits of flip chip.
 A comparison among the Wirebond, High-Lead Bump and APS Pillar Bump flip chip process is shown below.



The following table highlights the advantages of Pillar Bump flip chip process versus Wirebond and High-Lead process:

WIRE BOND QFN HIGH LEAD FC-QFN PILLAR BUMP FC-QFN
Requires Silver spot Plating Requires Organic Surface Protection Bare Copper Lead-Frame and No Plating or OSP Required
Requires Wire Bond Loop Height of 150-200 Microns Requires Solder Paste print on the Leads or Solder Mask Fluxing of the Pillar Bump during Die Placement (No Solder print needed)
Requires 0.6-1.0 mm Wire Bond Span No Lead Free Lead-Free Bump Available

The cross-section picture shows the Pillar Bump attached on a Bare Cu lead. Note that the solder spread is well controlled.

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